This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv

    Coverpoint mul_cg::cp_rs1                          75.00%        100    Uncovered            
    Coverpoint mul_cg::cp_rs2                          75.00%        100    Uncovered            
    Coverpoint mul_cg::cp_rd                           75.00%        100    Uncovered            
    Coverpoint mul_cg::cp_rs1_sign                    100.00%        100    Covered              
    Coverpoint mul_cg::cp_rs2_sign                    100.00%        100    Covered              
    Coverpoint mul_cg::cp_rd_sign                     100.00%        100    Covered              
    Coverpoint mulh_cg::cp_rs1                         75.00%        100    Uncovered            
    Coverpoint mulh_cg::cp_rs2                         75.00%        100    Uncovered            
    Coverpoint mulh_cg::cp_rd                          75.00%        100    Uncovered            
    Coverpoint mulh_cg::cp_rs1_sign                   100.00%        100    Covered              
    Coverpoint mulh_cg::cp_rs2_sign                   100.00%        100    Covered              
    Coverpoint mulh_cg::cp_rd_sign                    100.00%        100    Covered              
    Coverpoint mulhsu_cg::cp_rs1                       75.00%        100    Uncovered            
    Coverpoint mulhsu_cg::cp_rs2                       75.00%        100    Uncovered            
    Coverpoint mulhsu_cg::cp_rd                        75.00%        100    Uncovered            
    Coverpoint mulhsu_cg::cp_rs1_sign                 100.00%        100    Covered              
    Coverpoint mulhsu_cg::cp_rs2_sign                 100.00%        100    Covered              
    Coverpoint mulhsu_cg::cp_rd_sign                  100.00%        100    Covered              
    Coverpoint mulhu_cg::cp_rs1                        75.00%        100    Uncovered            
    Coverpoint mulhu_cg::cp_rs2                        75.00%        100    Uncovered            
    Coverpoint mulhu_cg::cp_rd                         75.00%        100    Uncovered            
    Coverpoint mulhu_cg::cp_rs1_sign                  100.00%        100    Covered              
    Coverpoint mulhu_cg::cp_rs2_sign                  100.00%        100    Covered              
    Coverpoint mulhu_cg::cp_rd_sign                   100.00%        100    Covered              
    Coverpoint div_cg::cp_rs1                          75.00%        100    Uncovered            
    Coverpoint div_cg::cp_rs2                          75.00%        100    Uncovered            
    Coverpoint div_cg::cp_rd                           75.00%        100    Uncovered            
    Coverpoint div_cg::cp_rs1_sign                    100.00%        100    Covered              
    Coverpoint div_cg::cp_rs2_sign                    100.00%        100    Covered              
    Coverpoint div_cg::cp_rd_sign                     100.00%        100    Covered              
    Coverpoint div_cg::cp_div_result                  100.00%        100    Covered              
    Coverpoint divu_cg::cp_rs1                         75.00%        100    Uncovered            
    Coverpoint divu_cg::cp_rs2                         75.00%        100    Uncovered            
    Coverpoint divu_cg::cp_rd                          75.00%        100    Uncovered            
    Coverpoint divu_cg::cp_rs1_sign                   100.00%        100    Covered              
    Coverpoint divu_cg::cp_rs2_sign                   100.00%        100    Covered              
    Coverpoint divu_cg::cp_rd_sign                    100.00%        100    Covered              
    Coverpoint divu_cg::cp_div_result                 100.00%        100    Covered              
    Coverpoint rem_cg::cp_rs1                          75.00%        100    Uncovered            
    Coverpoint rem_cg::cp_rs2                          75.00%        100    Uncovered            
    Coverpoint rem_cg::cp_rd                           75.00%        100    Uncovered            
    Coverpoint rem_cg::cp_rs1_sign                    100.00%        100    Covered              
    Coverpoint rem_cg::cp_rs2_sign                    100.00%        100    Covered              
    Coverpoint rem_cg::cp_rd_sign                     100.00%        100    Covered              
    Coverpoint rem_cg::cp_div_result                  100.00%        100    Covered              
    Coverpoint remu_cg::cp_rs1                         75.00%        100    Uncovered            
    Coverpoint remu_cg::cp_rs2                         75.00%        100    Uncovered            
    Coverpoint remu_cg::cp_rd                          75.00%        100    Uncovered            
    Coverpoint remu_cg::cp_rs1_sign                   100.00%        100    Covered              
    Coverpoint remu_cg::cp_rs2_sign                   100.00%        100    Covered              
    Coverpoint remu_cg::cp_rd_sign                    100.00%        100    Covered              
    Coverpoint remu_cg::cp_div_result                 100.00%        100    Covered              
